Cadence Delivers Encounter RTL Compiler Ultra with Support for VHDL; Cadence Provides Superior Quality of Silicon Throughout the Design Chain
SAN JOSE, Calif.—(BUSINESS WIRE)—Feb. 17, 2004—
Cadence Design Systems, Inc. (NYSE:CDN) today announced
Cadence(R) Encounter(TM) RTL Compiler Ultra synthesis tool with
support for VHDL. Encounter RTL Compiler synthesis is a key component
of the Encounter digital IC design platform and a critical step in the
fastest route to superior silicon. Supporting the Cadence
multi-language strategy, Encounter RTL Compiler Ultra synthesis works
with existing Verilog(R) and VHDL design flows to increase chip
performance, decrease design times, and provide the highest quality of
silicon (QoS) for Cadence customers throughout the design chain. QoS
measures a design's physical characteristics, in terms of area,
performance and power -- using wires.
Encounter RTL Compiler Ultra synthesis is used throughout the
design chain by Application Specific Integrated Circuit (ASIC) and
Intellectual Property (IP) vendors and Integrated Circuit (IC)
designers to help increase overall chip speed performance by 10
percent and improve area by 10 percent. In addition, runtime can be up
to three times faster compared to traditional tools.
"Cadence understands the significance of VHDL as a widely-used
language. Having access to Encounter RTL Compiler synthesis with VHDL
allows our engineers to utilize world-class technology to increase our
quality of silicon while improving our design time," said Dave
Chiappini, ASIC project director for Matrox, a leading supplier of
leading-edge graphics chips. "Graphics chips are typically large and
complex. In our current evaluation of Encounter RTL Compiler, we were
able to achieve up to 30 percent area savings on some designs, within
four days of installing the tool."
The new generation technology behind Encounter RTL Compiler Ultra
synthesis delivers global synthesis for timing closure using a unique
patented set of global focus algorithms that maximize the performance
of challenging designs. Encounter RTL Compiler synthesis fits into
existing flows and can adapt to old and new approaches to design.
In addition to the performance benefits, the Encounter RTL
Compiler product is drop-in compatible with existing solutions, making
it easy to evaluate and deploy into production flows for ASIC vendors,
IP suppliers and end users (see ARM/Cadence methodology release dated
Feb. 17, 2004). "In response to demand from IBM ASIC customers, the
Encounter RTL Compiler synthesis tool has been qualified in the IBM
ASIC tool flow and is now ready for customer engagement," said Tom
Reeves, vice president, ASIC product group, IBM Technology Group.
From an end-user perspective, the Encounter RTL Compiler tool's
interoperability with existing flows allows an end-user to evaluate
the tool through test designs that consider a variety of library, tool
and process technology options. "Our customers have been able to
evaluate Encounter RTL Compiler synthesis with Artisan libraries and
have seen excellent performance and area results," said Dhrumil
Gandhi, senior vice president of product technology at Artisan
Components.
Encounter RTL Compiler synthesis generates large-scale
transformations to the design by changing the global logic structure.
The patented set of global focus algorithms identify key leverage
regions in the design and work on multiple paths simultaneously. The
result is a better netlist for the back-end, in less time.
Quality of Silicon
In nanometer design, every aspect of a chip becomes dominated by
interconnect related parameters, design rules and failure mechanisms.
In order to truly understand the physical properties of a design at
130 nm and below, a new, meaningful metric for speed, area, power and
test must be applied. Quality of Silicon is the new generation metric
that exclusively handles measurements after wires.
Encounter RTL Compiler synthesis uses a unique, patented set of
global focus synthesis technologies that offer chip designers the
highest QoS in less time, and with less effort, while still being
backward compatible with old generation synthesis tools that are based
upon quality of results measurements. Armed with this algorithmic
advantage, Encounter RTL Compiler synthesis users enjoy a quantum
advantage over users of old generation, before-wires,
quality-of-results oriented measurement tools.
Availability
The Cadence Encounter RTL Compiler with support for VHDL and
mixed-languages is available immediately on Sun and Linux platforms.
About Cadence
Cadence is the largest supplier of electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics-based products. With
approximately 4,800 employees and 2003 revenues of approximately $1.1
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services is
available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks, and
Encounter is a trademark of Cadence Design Systems, Inc. All other
trademarks are the property of their respective owners.
Contact:
The Hoffman Agency for Cadence Design Systems
Carolyn Robinson, 408-975-3065
crobinson@hoffman.com
